As transistor size becomes smaller, more computational components, memories and lookup and decision engines can be integrated onto a single chip. This high integration allows for the ability to process more system tasks in parallel to achieve higher system performance. An on-chip network is an interconnection technique for a large number of lookup and decision engines on a single chip. The network includes multiple on-chip routers in which each on-chip router connects to the nearest neighboring on-chip router(s) in the network. Each lookup and decision engine is connected to one of the on-chip routers and an on-chip router can connect with multiple lookup and decision engines. Data communicated among lookup and decision engines are transferred through the network of the on-chip routers.